On July 15, 2026, the Union Cabinet chaired by the Prime Minister approved the “Semicon 2.0” program, marking the second phase of the India Semiconductor Mission (ISM). This expansion is backed by a substantial fiscal outlay of ₹1,27,500 crore (approximately US$13.23 billion). Building on the foundational work of the 2022 mission, Semicon 2.0 is designed to transition India from a nascent manufacturer to a resilient, end-to-end global semiconductor node, with the strategic goal of securing 75% of domestic chip requirements by 2030.
1. Breakdown of the Six Strategic Pillars
The transition to Semicon 2.0 reflects a shift from project-based support to a holistic ecosystem strategy, addressing upstream supply chain vulnerabilities and advanced technical nodes.
1.1 Semiconductor Chip Design & IP
Deepening the domestic design ecosystem is a priority for both strategic and commercial sectors. The policy shifts from flat grants (previously capped at ₹15 crore under ISM 1.0) to a more aggressive “co-investment” model.
- Support Mechanisms: For high-end design requirements exceeding ₹1,000 crore, the government will provide incentives through grants and equity, or royalty-based payments, in partnership with whitelisted venture capital funds.
- Risk Capital: Startups and MSMEs will receive seed money (Risk Capital) and access to Intellectual Property (IP) and Electronic Design Automation (EDA) tools.
- Inclusivity: Participation is now extended to Indian companies and those owned by Overseas Citizens of India (OCIs).
- DLI Scheme: Eligible entities will receive Deployment Linked Incentives (DLI) to offset the prohibitive costs of tape-outs.
1.2 Machines, Materials, and Specialty Gases
Recognizing that fabrication is impossible without a matured upstream, Pillar 1.2 represents a maturation toward “supply-chain resilience.” This new focus incentivizes the manufacturing and R&D of semiconductor production equipment, specialty chemicals, industrial gases, and electronic-grade materials. This move aims to develop a domestic precision manufacturing industry capable of integrating into global supply chains.
1.3 Fabrication Units (Fabs)
Semicon 2.0 aims to attract higher-density investments in silicon fabs, compound semiconductors, discrete components, and display fabs. A key technical benchmark is the Tata Electronics fab in Dholera, which targets the 28nm node—a versatile standard for power electronics and automotive applications—with a capacity of 50,000 wafer starts per month (WSPM).
1.4 ATMP and Advanced OSAT Packaging
India is positioning itself as an alternative global hub for Assembly, Testing, Marking, and Packaging (ATMP) and Outsourced Semiconductor Assembly and Testing (OSAT). The policy incentivizes a shift from conventional packaging to advanced packaging technologies (such as 3D heterogeneous integration), as global manufacturers seek production locations outside traditional East Asian hubs.
1.5 Research & Development (R&D)
The mission is pivotally moving from supporting legacy nodes (28nm-110nm) to “advanced nodes” (sub-7nm). This transition is facilitated through collaborations with global R&D centers, focusing on Intellectual Property (IP) generation and node migration to secure a place in the global technology roadmap.
1.6 Workforce and Talent Development
Talent development has shown rapid scaling, with 70,000 students already trained across 320 universities using industry-standard EDA tools. The mission is now expanding into specialized training for clean-room operations and fab construction to meet the labor demands of a fully operational ecosystem.
2. Semicon 2.0 Financial Support Framework
Financial support is disbursed on a pari-passu basis, ensuring government incentives are released in tandem with actual capital expenditure (Capex).
| Project Type | Capital Expenditure (Capex) Support |
| CMOS-based Silicon Fabs | 40% |
| Other Fabs (Compound, Discrete, Display) | 35% |
| Advanced Packaging (ATMP/OSAT) | 35% |
| Conventional Packaging (ATMP/OSAT) | 25% |
Track Record: Performance and Legacy of Semicon 1.0
The scale of Semicon 2.0 is validated by the momentum established during Phase 1, which successfully moved the industry from policy announcements to active commercial production.
- Total Committed Investments: ₹1.64 Lakh Crore (US$17.02 billion).
- Approved Manufacturing Units: 12 units, comprising one silicon fab, one silicon carbide (SiC) fab, one GaN micro-LED fab, and nine packaging units.
- Operational Status: Facilities by Micron, Kaynes, and CG Semi have already commenced commercial production.
- Design Ecosystem: 24 projects approved under the DLI scheme; 105 startups/MSMEs granted EDA tool access.
The scale of this mission is notably aggressive when compared to other simultaneous industrial pushes, such as the ₹10,000 Crore Biopharma SHAKTI Scheme, highlighting the government’s disproportionate focus on semiconductor sovereignty.
Geographic Distribution of Approved Projects
Approved projects are diversifying across several strategic regional hubs:
- Gujarat: 6 units, including the Tata Electronics-PSMC fab in Dholera (targeting 28nm) and OSAT units in Sanand and Surat (Suchi Semicon).
- Assam: Tata Semiconductor’s ATMP facility in Jagiroad—the first unit in the Northeast.
- Uttar Pradesh: HCL-Foxconn JV in Greater Noida, specifically for the production of 36 million Display Driver Chips (DDIC).
- Odisha: SicSem Private Limited (SiC fab) and 3D Glass Solutions (advanced packaging) in Bhubaneswar.
- Other States: Capacity expansion in Punjab (CDIL for discrete semiconductors) and Andhra Pradesh (ASIP Technologies OSAT unit).
Academic and Research Trajectory
The R&D ecosystem has undergone a “quiet evolution” since the establishment of the first Centers of Excellence in Nanoelectronics (CENs) at IIT Bombay and IISc Bangalore in 2006.
- Global Standing: By 2019, India ranked 3rd globally in contributions to IEEE Transactions on Electron Devices (TED), with the IIT System ranking 1st globally among organizations.
- Talent Breakdown: Research indicates high “frontline talent” (92% Indian first authors in TED), but highlights a “management gap” in industrial translation; for IEDM—a flagship industrial conference—Indian “Last Author” (science manager) representation falls to 56%.
- Incubation Timeline: The arXiv study shows a 6-year incubation period from infrastructure initiation to initial publications, followed by an additional 4 years (10 total) to achieve global R&D competitiveness.
Implementation Timeline
- Official Commencement: Fiscal Year 2026-27 (FY27).
- Mission Duration: Six years.
- Key Milestone: India’s first silicon fabrication plant (Tata-PSMC) is slated for commissioning in 2028, signaling the official entry into high-volume wafer production.
Official Source Citation
The following is the official government source used for the information provided above:
Official Source: India Semiconductor Mission. (2026). Semicon 2.0. Ministry of Electronics and Information Technology (MeitY), Government of India. https://ism.gov.in/schemes/semicon2.0/index
Leave a Comment